Position Description:

As a member of the DSP engineering group you will be respoible for verification of advanced DSP cores and their itruction set architectures and hardware implementatio. You will implement architectural simulation test benches in C/C++/RTL, write C/assembly language diagnostics, assertion checke or coverage monito to meet target verification goals. You will also assist with developing test pla, debugging failures and analyzing coverage information. You will work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.

Position Requirements:

? Knowledge of DSPs, itructio sets, computer arithmetic concepts, and processor architecture concepts

? Good knowledge of C (C++ will be a plus)

? Working knowledge of Verilog and popular EDA simulato and testbench methodologies

? Knowledge of scripting languages such as Makefile/Perl is desired

? Knowledge of assembly programming and programming in a high level language such as C

? Good English communication skills – both written and verbal

? Strong problem solving skills along with an ability to work independently and in cooperation with global teams

? MS degree in EE/CS with 3 to 8 yea industry experience required.